In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode

ABSTRACT

An in-plane switching mode liquid crystal display device. The device coprises first and second substrates, a plurality of gate and data bus lines formed on the first substrate to define a plurality of pixel regions, a common bus line aligned in each pixel regions of the first substrate, a thin film transistor (TFT) formed at each pixel regions of the first substrate, a data electrode which is formed on a gate insulator of the TFT and has a portion overlying the common bus line for forming a first storage capacitor, a passivation layer formed over the data electrode and the TFT, a common electrode which is formed on the passivation layer so as to overlap the gate and data bus lines and has a portion overlying the data electrode for forming a second storage capacitor, and a liquid crystal layer formed between the first and second substrates.

BACKGROUND OF THE INVENTION

A. Field of the Invention

The present invention relates to a liquid crystal display device, andmore particularly to an in-plane switching mode liquid crystal displaydevice.

B. Description of the Related Art

Recently, the thin film transistor liquid crystal display devices (TFTLCDS) have been used as display devices in such applications as portabletelevisions and notebook computers, but these TFT LCDs have smallviewing angles.

In order to solve this problem, twisted nematic LCDs having, forexample, optical compensation plates and multi-domains, have beenintroduced. In these LCDs, however, the color of the image is shiftedbecause the contrast ratio depends on the viewing angle direction.

For a wide viewing angle, the in-plane switching mode LCD is disclosed,for example, in JAPAN DISPLAY 92 page 547, Japanese Patent UnexaminedPublication No. 7-36058, Japanese Patent Unexamined Publication No.7-225388, and ASIA DISPLAY 95 page 707.

FIG. 1a and FIG. 1b are respectively plane and sectional views of theconventional in-plane switching mode liquid crystal display device (IPSmode LCD). FIG. 1b is a sectional view taken along line A-A′ of FIG. 1a.As shown in these figures, a gate bus line 1 and a data bus line 2 areformed on a first substrate 10, defining a pixel. Although only onepixel is shown in the figures, a liquid crystal display device generallyhas a plurality of pixels. A common bus line 3 is aligned in the pixel,being parallel to gate bus line 1. A thin film transistor (TFT) isdisposed at the intersection of gate and data bus lines 1 and 2. Asshown in FIG. 1b, the TFT comprises a gate electrode 5, a gate insulator12, a semiconductor layer 15, and an n⁺ semiconductor layer 16, a sourceelectrode 6, and a drain electrode 7. In the pixel, a data electrode 8and a common electrode 9 are formed parallel to data bus line 2. Aportion of data electrode 8 which overlaps common bus line 3 is formedto obtain a storage capacitor, which functions as maintaining a greylevel voltage applied into data electrode 8. Common electrode 9 isconnected to common bus line 3. Data electrode 8 is formed on gateinsulator 12 and is connected to drain electrode 7. The TFT, dataelectrode 8 and gate insulator 12 are covered with a passivation layer20. Thereon, a first alignment layer 23 a is coated to determine thealignment direction.

On a second substrate 11, a black mask 28 is formed to prevent a leakageof light through the regions of the TFT and gate and data bus lines 1and 2. Thereon, a color filter layer 29 and a second alignment layer 23b are formed. Between first and second substrates 10 and 11, a liquidcrystal layer 30 is formed.

When a voltage is applied to the conventional IPS mode LCD, electricfield parallel to substrates 10 and 11 is generated between data andcommon electrodes 8 and 9. Liquid crystal molecules in the pixel arerotated according to the electric field, controlling the amount of lightpassing through liquid crystal layer 30.

However, the conventional IPS mode LCD has the following problems.

First, because the area for storage capacitor occupies quite a portionof the pixel region and because the data and common electrodes are madeof opaque metals, the aperture ratio is lowered.

Second, because the electric field applied to the LC layer is weakenedby both gate insulator 12 and passivation layer 20 formed over twoelectrodes 8 and 9, the driving speed of the LC molecules is decreased,and consequently the driving voltage is increased.

Third, because data bus line 2 should be apart from the pixel region soas to avoid the crosstalk problem, the pixel region is decreased,thereby lowering the aperture ratio.

Fourth, when the black mask is formed on the second substrate, thefabricating cost is increased and the aperture ratio is lowered tocompensate for the imprecise lamination of the two substrates.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an in-plane switchingmode liquid crystal display device wherein the aperture ratio isimproved.

Another object of the present invention is to provide an in-planeswitching mode liquid crystal display device wherein the driving voltageis decreased.

A further object of the present invention is to reduce the fabricatingcost of provide an in-plane switching mode liquid crystal displaydevice.

Additional objects and advantages of the invention will be set forth inpart in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention will be realized and attained bymeans of the elements and combinations particularly pointed out in theappended claims.

To achieve the objects and in accordance with the purpose of theinvention, as embodied and broadly described herein, the in-planeswitching mode liquid crystal display device of the present inventioncomprises: a substrate; a plurality of gate and data bus lines over thesubstrate, defining a plurality of pixel regions; a common bus linealigned in the pixel regions; a gate insulator over the common bus line;a data electrode over the gate insulator and having a portion overlyingthe common bus line to form a first storage capacitor; a passivationlayer over the data electrode; and a common electrode over thepassivation layer at least partially overlying the gate and data buslines and at least partially overlying the data electrode to form asecond storage capacitor.

According to another aspect of the present invention, the in-planeswitching mode liquid crystal display device comprises: a substrate; aplurality of gate and data bus lines over the substrate, defining aplurality of pixel regions; a common bus line aligned in the pixelregions; a gate insulator over the common bus line; a thin filmtransistor coupled to each of the pixel regions and including at least apart of the gate insulator; a data electrode over the gate insulator andhaving a portion overlying the common bus line to form a first storagecapacitor; a passivation layer over the data electrode and the thin filmtransistor; a common electrode over the passivation layer and at leastpartially overlying the data electrode to form a second storagecapacitor; and a metal layer over the passivation layer and the thinfilm transistor.

According to a further aspect of the present invention, the in-planeswitching mode liquid crystal display device comprises: first and secondsubstrates having a plurality of pixel regions; a common bus linealigned in the pixel regions; a first insulating layer over the commonbus line; a data electrode over the first insulating layer and having aportion overlying the common bus line to form a first storage capacitor;a second insulating layer over the data electrode; a common electrodeover the second insulating layer, the common electrode having one ormore openings, at least one of the openings having a substantiallyrectangular shape with four corner areas, at least one corner area beingcut at an angle, and the common electrode having a portion overlying thedata electrode to form a second storage capacitor; and a liquid crystallayer formed between the first and second substrates.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description, serve to explain the principles of theinvention.

in the figures:

FIG. 1a and FIG. 1b are respectively plane and sectional views of theconventional in-plane switching mode liquid crystal display device;

FIG. 2a is a plane view showing a first embodiment of the presentinvention;

FIG. 2b and FIG. 2c are respectively sectional views taken along lineB-B′ and C-C′ of FIG. 2a;

FIG. 3 is a view showing the operation of liquid crystal molecules inthe first embodiment;

FIG. 4 is a view showing the alignment direction in the firstembodiment;

FIG. 5 is a plane view of the TFT array structure of the presentinvention;

FIG. 6a and FIG. 6b are respectively plane and sectional views showingthe structure of the IPS mode LCD according to the present invention;

FIG. 7 is a plane view of a second embodiment of the present invention;

FIG. 8 is a view showing the alignment direction and the direction offirst and second oblique sides of the second embodiment;

FIG. 9a and FIG. 9b are views showing the direction of electric fieldand the operation of LC molecules in the first and second embodimentsrespectively;

FIG. 10a is a plane view showing a third embodiment of the presentinvention;

FIG. 10b is a view showing the alignment direction and the direction offirst and second oblique sides of the third embodiment;

FIG. 11a is a plane view showing a fourth embodiment of the presentinvention;

FIG. 11b and FIG. 11c are respectively sectional views taken along linesE-E′ and F-F′ of FIG. 11a; and

FIG. 12 is a plane view showing a fifth embodiment of the presentinvention.

DETAILED DESCRIPTION

Hereinafter, in-plane switching mode LCDs according to the presentinvention are described in detail accompanying the figures.

FIG. 2a, FIG. 2b and FIG. 2c are views showing a first embodimentaccording to the present invention, where FIG. 2b and FIG. 2c arerespectively sectional views taken along line B-B′ and line C-C′ of FIG.2a. As shown in these figures, gate and data bus lines 101 and 102 areformed on a first substrate 110, defining a pixel. Although only onepixel is drawn in these figures, the liquid crystal display devicegenerally has a plurality of pixels. In the pixel, a common bus line 103is formed parallel to gate bus line 101. At the intersection of gate anddata bus lines 101 and 102, a thin film transistor (TFT) is formed asshown in FIG. 2b which comprises a gate electrode 105, a gate insulator112, a semiconductor layer 115, an n⁺ semiconductor layer 116, a sourceelectrode 106, and a drain electrodes 107. In the pixel, data and commonelectrodes 108 and 109 are disposed parallel to data bus line 102. Overthe TFT and data electrode 108, a passivation layer 120 is formed, andcommon electrode 109 is formed thereon to be parallel to data electrode108 and overlap gate and data bus lines 102 and 103. Over commonelectrode 109 and passivation layer 120, a first alignment layer 123 ais formed.

As in the conventional IPS mode LCD, data electrode 108 has a portionoverlapping common bus line 103 for obtaining a first storage capacitor(C_(st1)) as shown in FIGS. 2a and 2 c. In addition, common electrode109 has a portion overlapping data electrode 108 for obtaining a secondstorage capacitor (C_(st2)).

Common electrode 109 is connected to common bus line 103 through a firsthole 125 which is formed in passivation layer 120 and gate insulator(layer) 112. Common electrode 109 also overlaps gate and data bus lines101 and 102. Thus, it functions to block the electric effect of two buslines 101 and 102 to prevent the crosstalk problem.

Gate electrode 105, gate bus line 101, and common bus line 103 areformed by patterning double metal layers (Mo/Al) which is deposited bysputtering an Al layer having a thickness of 2000 Å and a Mo layerhaving a thickness of 1000 Å in the named order. Gate insulator 112 isformed thereon by depositing an inorganic insulating layer such assilicon nitride having a thickness of 4000 Å by a chemical vapordeposition method. A semiconductor layer 115 and an n⁺ semiconductorlayer 116 are formed by depositing and etching an amorphous silicon(a-Si) layer having a thickness of 1700 Å and an n⁺ a-Si layer having athickness of 300 Å. Data bus line 102, data electrode 108, sourceelectrode 106, and drain electrode 107 are formed by depositing andetching a Cr metal layer having a thickness of 1500 Å. Also, the gateand data bus line may be formed of high conductive metal layers such asMo metal layer, Mo/Al/Mo triple metal layers, or Cr/Al/Cr triple metallayers in order to prevent signal delay in the gate and data bus lineswhich is generated by being overlapped with the common electrode.

The TFT and data electrode 108 are covered with a passivation layer 120such as silicon oxide and silicon nitride having a thickness of 2000 Å.On passivation layer 120, common electrode 109 is formed by depositingand etching a transparent conducting layer such as indium tin oxide(ITO) having a thickness of 500 Å.

Over common electrode 109 and passivation layer 120, a first alignmentlayer 123 a is formed by coating polyimide or polyamide orphoto-alignment materials. The polyimide or polyamide alignment layer isrubbed to impart an alignment direction thereto. On the other hand, thephoto-alignment layer such as polyvinylcinnamate (PVCN) or polysiloxanebased materials is exposed to an ultraviolet light to impart analignment direction thereto.

As shown in FIG. 2c, data and common electrodes 108 and 109 haveportions for first and second storage capacitors whose capacitances areC_(st1) and C_(st2) respectively. Accordingly, the total storagecapacitance (C_(st)) in the present invention becomes the sum of storagecapacitances C_(st1) and C_(st2). The storage capacitor (C_(st)) isdouble the conventional storage capacitor (C_(st1)), so that the areafor storage capacitor can be reduced to half the conventional area,thereby improving the aperture ratio.

As shown in FIG. 2b, on a second substrate 111, a black mask 128 and acolor filter layer 129 are formed. An overcoat layer may be formedthereon to flatten and stabilize the surface. Black mask 128 prevents aleakage of light through the regions of TFT and gate, data and commonbus lines 101, 102, and 103. Black mask 128 is made of a Cr or a CrOxmetal layer having a thickness of 0.1 μm and a width of 10 μm. Colorfilter layer 129 has one of R, G, and B color filter elements in eachpixel. On color filter layer 129, a second alignment layer 123 b isformed by coating polyimide or photo-alignment materials. Secondalignment layer 123 b is rubbed or exposed to UV light to impart analignment direction. A liquid crystal layer 130 is inserted between twosubstrates 110 and 111 by injecting liquid crystal in vacuum state.

FIG. 3 is a view showing the operation of liquid crystal molecules inthe IPS mode LCD according to the present invention. FIG. 4 is a viewshowing the alignment direction, where the Y axis direction indicatesthe extension direction of data and common electrodes 108 and 109, andθ_(R) indicates the angle between the alignment direction and the X axisdirection, which is the extension direction of data bus line 102. When avoltage is not applied to the device, the liquid crystal molecules arealigned according to the alignment direction. When a voltage is appliedto the device, electric field parallel to the substrates is generatedbetween common and data electrodes 109 and 108, and thereby liquidcrystal molecules 132 rotates clockwise according to the electric field.In FIG. 3, a reference number 133 indicates the positions of the liquidcrystal molecules after applying the voltage.

FIG. 5 is a view showing the TFT array structure of the presentinvention. Gate and data bus lines 101 and 102 are connected to gate anddata driving circuits through gate and data pads 151 and 155respectively. Gate and data bus lines 101 and 102 are connected to agrounding wiring 165 through an electrostatic discharging circuit 167composed of TFT. Also common bus line 103 is grounded through common pad157.

Although not illustrated in the figure, gate, data and common pads 151,155 and 157 are made of first, second and third metal layers. The firstmetal layer is formed of Mo/Al double metal layers together with gateelectrode 105 and common bus line 103, as shown in FIGS. 2a, 2 b, and 2c. The second metal layer is formed of Cr together with source and drainelectrode 106 and 107. The third metal layer is formed of ITO togetherwith common electrode 109. In order to connect the pads to the drivingcircuits, it is necessary to etch gate insulator 112 and passivationlayer 120 in the pad region. The two insulating layers in the pad regionare etched when hole 125 is formed. In the prior art, an oxide layer isgenerated on the pads by the exposure to the air, causing a problem thatthe contacting electric resistance is increased when connecting the padsto the driving circuits. However, in this embodiment, because the thirdmetal layer of the pads is made of ITO to obtain an IOP (ITO OnPassivation) structure, the above-mentioned problem is not generated.

FIG. 6a and FIG. 6b are plane and sectional views showing the structureof the in-plane switching mode LCD consistent with the presentinvention, where FIG. 6b is a sectional view taken along line D-D′ ofFIG. 6a. As shown in these figures, gate and data driving circuits 150and 154 are disposed in a frame 145 outside display region 140. Gate anddata driving circuits 150 and 154 are connected to gate and data buslines 101 and 102 through gate and data pads 151 and 154 respectively. Abacklight housing 147 is disposed on the upper side of frame 145. Inbacklight housing 147, a backlight 148 is disposed to project a lightinto a liquid crystal panel 139 through a light pipe 149. Between lightpipe 149 and liquid crystal panel 139, a polarizer 135 is disposed topolarize the light linearly. An analyzer 136 is disposed on the front ofpanel 139.

The advantages of the first embodiment according to the presentinvention are summarized as follows.

First, passivation layer 120 and gate insulator 112 (shown in FIGS. 2band 2 c) do not absorb the electric field applied to liquid crystallayer 130 because common electrode 109 is disposed above two insulatinglayers 112 and 120. Accordingly, the driving voltage is lowered.

Second, because the areas for storage capacitor can be decreased, theaperture ratio is much more improved.

Third, because common electrode 109 overlaps gate and data bus lines 101and 102 to block the electric effect of two bus lines 101 and 102, thecrosstalk problem can be eliminated. Accordingly, the pixel region canbe enlarged, improving the aperture ratio.

Fourth, because common electrode 109 is formed of ITO to obtain an IOPstructure, the contacting electric resistance between the pads and thedriving circuits is decreased, and the aperture ratio is improved.

FIG. 7 is a view showing a second embodiment of the present invention.Hereinafter, constituent elements similar to those of the firstembodiment are denoted by the same reference numbers. As shown in thisfigure, this embodiment differs from the first embodiment in that acommon electrode 209 has first and second oblique sides 210 and 211.FIG. 8 is a view showing the alignment direction and the direction ofthe first and second oblique sides of the second embodiment, where Yaxis indicates the extension direction of the data electrode 108. Inregion A of FIG. 7, first oblique side 210 is inclined counterclockwisefrom the X axis with an angle θ_(A). In region B, second oblique side210 is inclined clockwise from the X axis with an angle θ_(B). Thealignment direction is determined to be inclined counterclockwise to Xaxis direction with an angle θ_(R) in the range of 0 to 90°. Angle θ_(A)is determined to be in the range of θ_(R) to 90°. The angle θ_(B) isdetermined to be in the range of 90°−θ_(R) to 90°. The figures show acase where the angle θ_(R) is larger than 45°, and therefore the angleθ_(A) is larger than the angle θ_(B). On the contrary, when the angleθ_(R) is smaller than 45°, the angle θ_(B) is determined to be largerthan the angle θ_(A).

The object of this embodiment is to prevent the problem of the firstembodiment, in which disclination may be generated in the region wherecommon electrode 209 crosses with data electrode 109.

In the first embodiment, the electric field is generated between commonand data electrodes 108 and 109 as shown in FIG. 9a. In the middleregion of the opening portion, the direction of electric field isperpendicular to the extension direction of electrodes 108 and 109. Whenvoltage is applied to the device, in the middle region, LC molecules 132are given a clockwise turning force according to the electric fieldperpendicular to the extension direction of electrodes 108 and 109, andthereby they rotate clockwise to be aligned perpendicular to theextension direction of the electrodes. On the other hand, in regions Aand B where common electrode 109 crosses with data electrode 108, anelectric field is deformed not to be perpendicular to the extensiondirection of electrodes 108 and 109. When the voltage is applied toelectrodes 108 and 109, in regions A and B, LC molecules 132 are alignedto be different from the middle region. Particularly in the regionbounded by chain lines, the LC molecules are given with acounterclockwise turning force according to the deformed electric field,and thereby they rotate in opposite direction to those in the middleregion. Consequently, in the border region denoted by chain lines, thealignment of LC molecules 132 is not defined, thereby generatingdisclination. Particularly when using liquid crystal having a lowviscosity for lowering the driving voltage, since the interactionbetween LC molecules 132 is weak, a possibility of generating thedisclination is increased to deteriorate the image quality. In thisfigure, reference number 133 denotes LC molecules after applying thevoltage.

However, in the second embodiment, since common electrode 209 has firstand second oblique sides 210 and 211, as shown in FIG. 7, the electricfield is slightly deformed in regions A and B, as shown in FIG. 9b. Theelectric field gives a clockwise turning force to LC molecules 232 inregions A and B. Accordingly, although using liquid crystal having a lowviscosity for lowering the driving voltage, LC molecules 232 in regionsA and B rotate in the same direction with those in the middle region,thereby preventing the disclination. In FIG. 9b, reference number 233denotes LC molecules after applying the voltage.

The second embodiment has an aperture ratio lower than the firstembodiment, and however has a more improved image quality by preventingthe disclination. In this case, it is preferable to form commonelectrode 209 out of ITO for improving the aperture ratio.

FIG. 10 is a view showing a third embodiment. This embodiment is similarto the second embodiment except for angles θ_(A) and θ_(B) of commonelectrode 309. In this embodiment, angles θ_(A), θ_(B) and θ_(R) areapproximately 45°, 45°, and 75° respectively. In region B, because angleθ_(B) is in the range of 90°−θ_(R), to 90°, the LC molecules are givenwith a clockwise turning force, thereby not generating the disclination.On the other hand, in region A, since the angle θ_(A) is out of therange of θ_(R) to 90°, the LC molecules are given a counterclockwiseturning force.

However, the disclination is not generated in the region A because thereis an interaction between the liquid crystal molecules when using ausual liquid crystal.

FIGS. 11a, 11 b, and 11 c are plane and sectional views showing thefourth embodiment, where FIGS. 11b and 11 c are sectional views takenalong lines E-E′ and F-F′ of FIG. 11a respectively.

In this embodiment, as shown in these figures, data and commonelectrodes 108 and 409 have portions for first and second storagecapacitors as in the previous embodiments. This embodiment differs fromthe previous embodiments in that the common electrode does not overlapgate and data bus lines 101 and 102, and a light shielding electrode 160is formed on passivation layer 120 in the region of the TFT. Commonelectrode 409 and light shielding electrode 160 are formed together bysputtering and etching Mo metal layer having a thickness of 1000 Å.Because light shielding electrode 160 functions as a black mask for theTFT, as shown in FIG. 11b, the black mask is not formed in the region ofTFT. To obtain an IOP structure, two electrodes 409 and 160 are formedof metal layers including ITO, and it is preferable that they are formedof a double layer ITO/Mo which is formed by depositing Mo metal layerand ITO in the named order. Light shielding electrode 160 is formed tooverlap a portion of gate bus line 101 so as to be connected with gatebus line 101 through a second hole 161 formed in gate insulator 112 andpassivation layer 120. Accordingly, light shielding electrode 160 isprovided with the same voltage as gate electrode 105.

In this embodiment, light shielding electrode 160 overlaps the TFT withpassivation layer 120 interposed therebetween in order to prevent alight incident on semiconductor layer 115 of the TFT. Accordingly, thereis no need to form a black mask in the region of TFT, decreasing thefabricating cost. Further, the leakage current is prevented which isgenerated by excitation of semiconductor layer 115 when semiconductorlayer 115 is exposed to light, so that a backlight having a high lightintensity can be used improving the luminosity of the device.

In addition, since light shielding electrode 160 is connected with thegate bus line for obtaining the same voltage as gate electrode 105, itfunctions as a back gate electrode increasing the switching current ofthe TFT. Accordingly, switching speed of the TFT is increased so thatthe same switching speed as the prior art can be obtained using TFT ofrelatively small size.

FIG. 12 is a view showing a fifth embodiment. As shown in this figure,this embodiment is similar to the fourth embodiment except that a commonelectrode 509 overlaps gate and data bus lines 101 and 102 as in thefirst, second, and third embodiments.

Common electrode 509 and a light shielding electrode 260 are formed ofopaque metals as the fourth embodiment, and function as a lightshielding layer so that there is no need to form a black mask in theregions of the TFT, and two bus lines 101 and 102. Accordingly, thefabricating cost for the black mask is reduced, and prevented is theconventional problem in that the aperture ratio is lowered by having tocompensate for imprecise lamination when forming the black mask on thesecond substrate. Further, as in the fourth embodiment, light shieldingelectrode 260 prevents a light incident on the active layer.

In the first, second, third, and fifth embodiments, a parasiticcapacitor may be formed between the common electrode and the gate anddata bus lines, causing the signal delay in the two bus lines. Thissignal delay problem can be eliminated by forming the gate and data buslines out of low resistance metal layers such as Mo metal layer,Mo/Al/Mo triple metal layers or Cr/Al/Cr triple metal layers.

The present invention is characterized in that the common electrode isformed on passivation layer 120, and the data and common electrodes haveportions for first and second storage capacitors. Accordingly,passivation layer 120 and gate insulator 112 do not absorb the electricfield applied to liquid crystal layer 130 because the common electrodeis disposed above two insulating layers 112 and 120. Accordingly, thedriving voltage is lowered. Further, because the areas for storagecapacitor can be decreased, the aperture ratio is much more improved.Furthermore, because the common electrode is formed out of ITO forobtaining IOP structure, the contacting electric resistance between thepads and the driving circuits 16 decreased as well as the aperture ratiois improved.

In first, second, third, and fifth embodiments according to the presentinvention, because the common electrode overlaps the gate and data buslines to block the electric effect of the two bus lines, the crosstalkproblem can be removed. Accordingly, the pixel region can be enlargedimproving the aperture ratio.

In fourth and fifth embodiments, the light shielding electrode functionsas a back gate electrode for increasing the switching speed of TFT, andprevents a leakage current caused by excitation of the active layer.Particularly in the fifth embodiment, since the light shieldingelectrode and the common electrode function as a black mask, there is noneed to form the black mask in the regions of TFT and the two bus lines101 and 102, removing the problems generated when forming the black maskon the second substrate.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the in plane switching modeliquid crystal display device of the present invention and inconstruction of this device without departing from the scope or spiritof the invention.

Other embodiments of the invention will be apparent to those skilled inthe art from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A liquid crystal display device, comprising: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in said pixel regions; a gate insulator layer over said common bus line; a data electrode over said gate insulator layer and having a portion overlying said common bus line to form a first storage capacitor; a passivation layer over said data electrode; and a common electrode over said passivation layer at least partially overlying said gate and data bus lines and at least partially overlying said data electrode to form a second storage capacitor.
 2. The device according to claim 1, wherein said common electrode is conductively coupled to said common bus line through a first hole in said gate insulator layer and said passivation layer.
 3. The device according to claim 1, wherein said gate and data bus lines include highly conductive metal.
 4. The device according to claim 3, wherein said gate and data bus lines include one of a Mo metal layer, Mo/Al/Mo triple metal layers, or Cr/Al/Cr triple metal layers.
 5. The device according to claim 1, wherein said common electrode includes indium tin oxide.
 6. The device according to claim 1, wherein said common electrode has one or more openings, one or more of said one or more openings having a substantially rectangular shape with one or more of the four corner areas of said rectangular shape cut at an angle.
 7. The device according to claim 6, wherein said common electrode includes indium tin oxide.
 8. The device according to claim 1, further comprising an alignment layer over said common electrode and said passivation layer.
 9. The device according to claim 8, wherein said data electrode extends in a first direction, and wherein said alignment layer has an alignment direction inclined counterclockwise at a first non-zero angle θ₁ relative to a second direction perpendicular to said first direction.
 10. The device according to claim 9, wherein said first angle θ₁ is in the range of 45° to 90°.
 11. The device according to claim 9 wherein said common electrode has one or more openings, one or more of said one or more openings having a polygonal shape with at least six sides, four sides being substantially rectangular, a first angled side connecting a first one of the rectangular sides to a second one of the rectangular sides, and a second angled side connecting the first one of the rectangular sides to a third one of the rectangular sides, said first angled side inclined counterclockwise relative to said second direction at a second angle θ₂ and said second angled side inclined clockwise relative to said second direction at a third angle θ₃.
 12. The device according to claim 11, wherein said second angle θ₂ is in the range of said first angle θ₁ to 90°.
 13. The device according to claim 11, wherein said third angle θ₃ is in the range of 90°−θ₁ to 90°.
 14. The device according to claim 11, wherein said first angle θ₁ is approximately 75°.
 15. The device according to claim 11, wherein said second angle θ₂ is approximately 45°.
 16. The device according to claim 11, wherein said third angle θ₃ is approximately 45°.
 17. The device according to claim 8, wherein said alignment layer includes one of polyimide, polyamide, or polyvinylcinnamate or polysiloxane based materials.
 18. The device according to claim 1, further comprising: a thin film transistor coupled to each of said pixel regions, at least partially including said gate insulator layer; and a metal layer over said passivation layer and overlying said thin film transistor.
 19. The device according to claim 18, wherein said metal layer and said common electrode include a same metal.
 20. The device according to claim 18, wherein said metal layer and said common electrode include Mo.
 21. The device according to claim 18, wherein said metal layer and said common electrode include indium tin oxide.
 22. The device according to claim 18, wherein said metal layer and said common electrode include a double metal layer ITO/Mo.
 23. The device according to claim 18, wherein said metal layer is conductively coupled to said gate bus line through a second hole in said gate insulator layer and said passivaton layer.
 24. The device according to claim 23, wherein said metal layer overlaps a portion of said gate bus line, and said second hole is formed in said overlying portion.
 25. An liquid crystal display device, comprising: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in said pixel regions; a gate insulator layer over said common bus line; a thin film transistor coupled to each of said pixel regions and including at least a part of said gate insulator layer; a data electrode over said gate insulator layer and having a portion overlying said common bus line to form a first storage capacitor; a passivation layer over said data electrode and said thin film transistor; a common electrode over said passivation layer and at least partially overlying said data electrode to form a second storage capacitor; and a metal layer over said passivation layer and said thin film transistor.
 26. The device according to claim 25, wherein said common electrode is condurctively coupled to said common bus line through a first hole in said gate insulator layer and said passivation layer.
 27. The device according to claim 25, wherein said metal layer and said common electrode include a same metal.
 28. The device according to claim 25, wherein said metal layer and said common electrode include Mo.
 29. The device according to claim 25, wherein said metal layer and said common electrode include indium tin oxide.
 30. The device according to claim 25, wherein said metal layer and said common electrode include a double metal layer ITO/Mo.
 31. The device according to claim 25, wherein said metal layer is conductively coupled to said gate bus line through a second hole formed in said gate insulator layer and said passivation layer.
 32. The device according to claim 31, wherein said metal layer overlaps a portion of said gate bus line, and said second hole is formed in said overlying portion of said gate insulator layer and said passivation layer.
 33. A liquid crystal display device, comprising: first and second substrates having a plurality of pixel regions; a common bus line aligned in said pixel regions; a first insulating layer over said common bus line; a data electrode over said first insulating layer and having a portion overlying said common bus line to form a first storage capacitor; a second insulating layer over said data electrode; a common electrode over said second insulating layer, said common electrode having one or more openings, at least one of said openings having a polygonal shape with at least five sides, four sides being substantially rectangular and an angled side connecting one of the rectangular sides to another of the rectangular sides, and said common electrode having a portion overlying said data electrode to form a second storage capacitor; and a liquid crystal layer formed between said first and second substrates. 